SPU Mark II - Architecture

Overview

This is the documentation for the SPU Mark II instruction set architecture. It is a stack based 16 bit processor that features a highly configurable instruction set.

Table Of Contents

Documentation Style

Numbers

Numbers are documented in three ways:

Decimal numbers are written the usual style. Hexadecimal numbers are prefixed by a 0x. Binary numbers are postfixed with a subscript ₂. If both decimal and binary notation are given, the decimal notation is postfixed with a subscript ₁₀ to make the difference clear.

Examples:

• Decimal numbers: 10, 23, 44₁₀
• Hexadecimal: 0x10, 0xFF, 0xCC3D
• Binary: 10₂, 1100101₂
• Mixed binary and decimal: 10₂ (2₁₀), 1100₂ (12₁₀)

Bit Ranges

This document uses some special notations to define bit ranges or indices.

[n] is a placeholder for the nth bit in a word.

[n:m] is a placeholder for the bit range from the nth (highest significant bit) to the mth (lowest significant bit).

So [3] means the the bit with the significance of 2³ and [7:4] is the upper nibble of a 8 bit word.

Wording

Undefined (value)

If a value is defined undefined, its initial value may be any possible value. The value may change between power cycles or even after a reset. Each bit must be considered random.

Undefined behavior

Undefined behavior is used similar to the way the C standard uses this word. It means that if a situation happens where undefined behavior would occur, the results of the operation may be anything. This can be a no-op, any state or memory change or even a CPU hang or hard reset (may even requires a power cycle).

CPU Variants

This document specifies two different variants for the SPU Mark II architecture:

• SPU Mark II
• SPU Mark II-L

The SPU Mark II-L is a reduced version of the default instruction set and features no interrupt handling, thus making an implementation of the ISA much easier.

SPU Mark II Architecture

The SPU Mark II (Stack Processing Unit Mark II) is a 16 bit processor that, in contrary to the most popular CPUs, works primarily with a stack instead of registers. It features a RISC instruction set with highly configurable instructions. Although being a stack processor it still requires some basic registers to work. These registers are either accessed indirectly (like the IP register) or by special instructions (like BP or SP register).

Each instruction is composed of a configuration part and a command part. Commands are the actual function of the instruction like STORE8 or MUL. Each command has two input variables input0 and input1 which contain the two command parameters. A command also has an output value.

In which way the command parameters are filled and the result is processed is defined by the configuration bits of the instruction. These bits allow conditional execution, input parameter modification, affect flags and define how the result of the command is processed.

As each instruction may be conditional, there are no special conditional jump commands. In fact, there isn't even a jump command at all. A jump is done by taking the output of a command to be the next instruction pointer.

Thus, the most simple COPY command can be used already for a whole set of different operations: jmp $imm, push $imm, pop and many more.

Basic Properties

Word Encoding and Signedness

The SPU Mark II uses the little endian encoding, so the less significant byte is at the lower address, the more significant byte at the higher address.

Integer arithmetic uses two-complement signed integers. This allows most arithmetic instructions to be used with signed and unsigned values.

Memory Access

The cpu only allows aligned memory access for word access. Unaligned word access must be programmed manually.

CPU Registers

Stack Pointer (SP)

16 bit register storing the address of the topmost value of the stack. The stack grows downwards, so a push operation decrements the SP by two and then stores a value to the decremented address. A pop or peek operation reads the value from SP, and for pop, SP will be incremented by 2.

Initial Value: Undefined

Base Pointer (BP)

16 bit register that may be used for indirect addressing via GET and SET commands and may be used as a frame pointer or index register.

Initial Value: Undefined

Instruction Pointer (IP)

16 bit register pointing to the instruction to be executed next.

Initial Value: Undefined

Flag Register (FR)

16 bit register saving CPU state and interrupt system

Initial Value: 0x0000

Note: The flags I[3:0] are not available in SPU Mark II-L

Interrupt Register (IR)

16 bit register storing internal interrupt information.

Initial Value: 0x0001 (Reset interrupt triggered)

Note: Not available in SPU Mark II-L

Instruction Encoding

Instructions use 16 bit opcodes organized in different bit fields defining the behaviour of the instruction.

Conditional Execution

This field determines when the command is executed or ignored. The execution is dependent on the current state of the flags.

This allows conditional execution of all possible opcodes.

Argument Input 0 and 1

These two fields define what arguments are provided to the executed command.

Zero means that the argument will be zero, Immediate means that it will be fetched from the instruction pointer (it is located behind the opcode in memory). Peek will take the argument from the stack top, but won't change the stack and Pop will take the argument from the stack top and decreases the stack pointer.

input0 is fetched before input1 so when both arguments pop a value, input0 receives the stack top and input1 receives the value one below the stack top. Likewise, when both arguments use the Immediate option, the value for input0 must located directly after the opcode, input1 directly after input0.

Flag Modification

When the flag modification is enabled, the current flags will be overwritten by this command. Otherwise the flags stay as they were before the instruction.

The flags are modified according to this table:

Result Output

Each command may output a value which can be processed in various ways. The output could be pushed to the stack, the command could be made into a jump or the output could be ignored.

For Jump Relative, the instruction pointer will point to the next instruction plus output words. output is considered a two-complements signed number. This differs from the Jump behavior which takes an address, not a word offset.

Commands

Commands are what define the core behaviour of the opcode. They allow arithmetics, modification of memory, changing system registers and so on.

Some hints on notation:

• MEM16[x] is the 16 bit word at address x
• MEM8[x] is the 8 bit word at address x

MUL, DIV and MOD use signed values as input and output. It is not possible to get the upper 16 bit of the multiplication result.

Memory Access

Only 2-aligned access to memory is possible with code or data. Only exception are the STORE8 and LOAD8 commands which allow 1-aligned memory access.

When accessing memory with alignment, the least significant address bit is reserved and must be 0. If the bit is 1, the behavior is undefined.

Fetch-Execute-Cycle

This pseudocode documents what the CPU does in detail when execution a single instruction.

​x
1
if (IR & 1) != 0:
2
  IP := fetch(0x0000)
3
  FR := 0x0000
4
  IR := 0x0000
5
​
6
while IR != 0:
7
  intr_bit := indexOfHighestSetBit(IR)
8
  IR &= ~(1<<intr_bit)         # clear "interrupt triggered"
9
  if intr_bit < 4 or (FR & (1<<intr_bit)) != 0: # if interrupt is not masked
10
    push(IP)
11
    IP := fetch(2 * intr_bit)   # fetch ISR handler
12
    if intr_bit >= 4:           # if interrupt is maskable
13
      FR &= ~(1<<intr_bit)      # unmask interrupt
14
​
15
instruction := fetch(IP)
16
IP += 2
17
​
18
if isExecuted(instruction, FR):
19
  input0 := fetchInput(instruction.input0)
20
  input1 := fetchInput(instruction.input1)
21
  
22
  output := instruction.command(input0, input1)
23
  
24
  select instruction.output:
25
    when 'push':
26
      push(output)
27
    when 'discard':
28
      # ignore
29
    when 'jmp':
30
      IP := output
31
    when 'rjmp':    
32
      IP += 2 * output
33
​
34
  if instruction.modifyFlags:
35
    FR.Z = (output == 0x0000)
36
    FR.N = (output >= 0x8000)
37
else
38
  if instruction.input0 == IMM:
39
    IP += 2
40
  if instruction.input1 == IMM:
41
    IP += 2

TODO: Add handling of BUS fault!

For the non-interrupt version, the state machine is simpler:

xxxxxxxxxx
31
1
if RST is high:
2
  IP := 0x0000
3
  FR := 0x0000
4
​
5
instruction := fetch(IP)
6
IP += 2
7
​
8
if isExecuted(instruction, FR):
9
  input0 := fetchInput(instruction.input0)
10
  input1 := fetchInput(instruction.input1)
11
  
12
  output := instruction.command(input0, input1)
13
  
14
  select instruction.output:
15
    when 'push':
16
      push(output)
17
    when 'discard':
18
      # ignore
19
    when 'jmp':
20
      IP := output
21
    when 'rjmp':    
22
      IP += 2 * output
23
​
24
  if instruction.modifyFlags:
25
    FR.Z = (output == 0x0000)
26
    FR.N = (output >= 0x8000)
27
else
28
  if instruction.input0 == IMM:
29
    IP += 2
30
  if instruction.input1 == IMM:
31
    IP += 2

Interrupt handling

Note: Interrupt handling is not available in SPU Mark II-L

The SPU Mark II provides 8 possible interrupts, four unmasked and four masked interrupts.

When an interrupt is triggered the CPU pushes the current instruction pointer to the stack and fetches the new instruction Pointer from the interrupt table. Then the flag in the Interrupt Register is cleared as well as the mask bit in the Flag Register (if applicable).

The reset interrupt is a special interrupt that does not push the return address to the stack. It also resets the Interrupt Register and the Flag Register.

Masking

If an interrupt is masked via the Flag Register (corresponding bit is 0) it won't be triggered (the Interrupt Register bit can't be set).

Interrupt Table

It is possible to assign each interrupt another handler address. The entry points for those handlers are stored in the Interrupt Table at memory location 0x0000:

Reset

This interrupt resets the CPU and defines the program entry point.

NMI

This interrupt is the non-maskable external interrupt. If the NMI pin is signalled, the interrupt will be triggered.

BUS

This interrupt is a non-maskable external interrupt.

The BUS interrupt is meant for an MMU interface and will prevent the currently executed instruction from having any side effects.

Remarks: It is required that the BUS interrupt happens while doing a memory operation. If after a memory read or write cycle the BUS pin is signalled, the CPU will assume as bus error and will trigger this interrupt.

ARITH

This interrupt is triggered when an error happens in the ALU. The reasons may be:

• Division by zero

IRQ

This interrupt is the maskable external interrupt. If the IRQ pin is signalled, the interrupt will be triggered.

Priorities

Before execution of each instruction the cpu checks if any interrupt is triggered. The handler for the lowest interrupt triggered will then be activated.

Chip I/Os

• 16 output address lanes
• 16 in/out data lanes
• output WE, RE signal
• input HOLD signal
• input CLK signal
• input RST signal
• input NMI signal
• input BUS signal
• input IRQ signal
• output TYPE signal (tells if memory access is for code or data)

Changelog

v1.8

• Removes NEG command
• Replaces free command slot with SIGNEXT
• Changes pseudo code for Fetch-Execute-Cycle examples to a python-like language
• Improves register description for BP
• Improves register description for SP
• Adds some clarification on the pseudo code in the Command table

v1.7

• Makes frset, spset, bpset return the previous value instead of the newly set. This allows improved or shorting handling of safed parameters.

v1.6

• Fixed typo in IP description

v1.5

• Textual architecture description
• Improves overall document quality.
• Introduces SPU Mark II-L (Version with no interrupt handling)
• FRGET now also provides a masked register access

v1.4

• Reorderes IRQ table
• FIX: Missing interrupt 6 from IRQ table
• Adjusts IR, FR
• Makes BUS nonmaskable
• Allows FRSET to have a masked register access

v1.3

• Defines unaligned memory access undefined behaviour.
• Packs all IRQs into a single one. Requires use of a memory mapped interrupt controller, but is ultimately less limiting.
• Reduces interrupt count to 8 (still two reserved interrupts)
• Adds interrupt descriptions.
• Makes BUS interrupt an external interrupt for a MMU
• Makes BUS prevent all effects from the current instruction

v1.2

• Adds preliminary I/O description

v1.1

• Adds FR, BP, SP, IP register names to register description
• Adds FRGET, FRSET instruction
• Introduces interrupt handling description

v1.0

• Initial version

TODO

• Further define HOLD line
• Consider "prefetch-queue" for instructions
• Document: No special I/O commands, only MMIO
• Document: Word Encoding = "Little Endian", so bits 0...7 is actually "lower" byte